RISClownin: custom RISC-V CPU

Description

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Over the course of Intro to Computer Architecture (18447) at CMU, I worked alongside Ankita Chatterjee and Bharathi Sridhar to create a custom RISC-V CPU implementation in SystemVerilog. Over the course of five assignments, we handwrote the initial five stage pipeline (fetch, decode, execute, memory, writeback) and gradually added more features. Our CPU is supports 32 bit integer RISC-V instructions, including all arithmetic, control flow, load/store instructions in immediate/register formats. The design was tested with gcc-generated code.

Features include:

• Pipelining and stalls
• Data forwarding
• RAW hazard detection
• Hysteresis branch prediction, with a branch target buffer (BTB)
• Return address stack (RAS)
• Parameterizable set-associative cache

Ultimately, in our class's RISC-V performance competition, when the memory stage was lengthened to an 8 cycle latency, our cache was instrumental in allowing us to place higher in the rankings. Additionally, in the final competition, we refactored our forwarding logic, which was our critical path at the time. This pivot allowed us to radically increase our design's clock frequency from before. Above is our diagram for the complete design. To abide by CMU's academic integrity policy, I do not have the code implementation for this project available.